The present invention is concerned with an electronic circuit that facilitates high voltage long term reliable operation of transistors in a standard low-voltage, sub-micron, complementary metal oxide semiconductor (CMOS) process.
In conventional CMOS circuits it frequently happens that during normal operation the maximum gate-source, gate-drain or drain-source voltages of the n-channel and p-channel transistors are sometimes substantially equal to the supply voltage. For example, such a situation occurs when operating a standard CMOS inverter. When transistors are fabricated in a standard sub-micron CMOS process (for example, with feature size below 0.8 xcexcm and gate-oxide thickness less than 150 xc3x85), and the supply voltage is sufficiently large (for example, over 5V), both n-channel and p-channel transistors suffer from hot-carrier degradation and gate-drain/gate-source overlap oxide breakdown While such effects can be avoided by either decreasing the supply voltage, or using a larger dimension fabrication process, it is frequently inconvenient to do either. For example it may be that only one supply rail is readily available or that space constraints require a sub-micron process.
In U.S. Pat. No. 5,726,589 there is described an output driver circuit for a semiconductor chip in which an N-channel transistor is protected from hot-carrier degradation by delaying the xe2x80x9cturning onxe2x80x9d of the transistor until the drain-source voltage has dropped below the characteristic hot-electron operation voltage. However, such a circuit does not protect its transistors (both P-channel and N-channel) from gate-oxide dielectric breakdown under high voltage stress.
In U.S. Pat. No. 5,369,312 a circuit technique is disclosed by which an N-channel transistor is protected from hot-carrier degradation by connecting two transistors in cascode with a third transistor to bias the intermediate node voltage roughly mid-way between the full supply voltage. However the circuit disclosed does not provide protection against gate-oxide breakdown under high voltage stress.
In U.S. Pat. No. 4,967,103 a circuit is described for avoiding hot-carrier degradation in a N-channel to N-channel push-pull inverter. Once again though, the circuit does not address the problem of gate-oxide dielectric breakdown.
It is an object of the present invention to provide a CMOS transistor circuit which avoids gate-oxide dielectric breakdown and preferably hot carrier degradation for both N and P transistors.
The present invention provides, in an electrical circuit fabricated using a sub-micron CMOS process of the type incorporating a first at least one CMOS transistor having a gate connected to a node taking a range of voltages and susceptible to hot carrier degradation and gate-oxide dielectric breakdown when operated at a first voltage level, the improvement comprising; connected between said gate and said node a second transistor biased at a voltage less than said first voltage level in an arrangement reducing the maximum voltage across the gate of said first transistor during operation of said circuit thereby avoiding said gate-oxide dielectric breakdown when operated at said first voltage level.
Preferably said improvement further comprises a third transistor biased and connected to a non-gate terminal of said first transistor in an arrangement avoiding said hot carrier degradation of said first transistor.
According to a further aspect of the invention there is provided in a CMOS inverter circuit designed for powering by a first voltage rail at potential Vdd and a second voltage rail at potential Vss being less than Vdd and having a first transistor of a first channel type connected to one of said first and second voltage rails and a second transistor of a complementary channel type connected to the other of said first and second voltage rails, the drain terminals of said first and second transistors connected to each other thereby forming an output node and the gates of said first and second transistors connected to each other thereby forming an input node and wherein upon applying voltage transitions between Vdd and Vss to said input node, said first and second transistors are subjected to gate-oxide dielectric breakdown and hot carrier degradation, the improvement comprising:
a third transistor of the same channel type connected between the gate of said first transistor and said input node, said third transistor having a gate biased at a voltage between Vss and Vdd thereby avoiding said gate-oxide dielectric breakdown of said first transistor.
Preferably said improvement further comprises a fourth transistor connected between the drain of said second transistor and said output node, said fourth transistor having a gate biased at a voltage between Vss and Vdd thereby avoiding said hot carrier degradation of said first transistor.
Preferably said improvement further comprises a fifth transistor connected between the drain of said first transistor and said output terminal, said fifth transistor having a gate biased at a voltage between Vss and Vdd thereby avoiding said hot carrier degradation of said first transistor.